ATMEGA128L-8MU

Product Summary

The ATmega128 is 100% p in compat ible wi th ATmega103, and can replace the
A Tmeg a 10 3 on c u r re n t P r i n t ed Ci r c u i t B o a rd s .
B y p r o g r a m m i n g t h e M 1 0 3 C f u s e , t h e A T m e g a 1 2 8 w i l l b e c o m p a t i b l e w i t h t h e
ATmega103 regards to RAM, I/O pins and interrupt vectors as described above. However, some new features in ATmega128 are not available in this compatibility mode,
these features are listed below:
One USART instead of two, Asynchronous mode only. Only the eight least
significant bits of the Baud Rate Register is available.
One 16 bits Timer/Counter with two compare registers instead of two 16-bit
Timer/Counters with three compare registers.
Two-wire serial interface is not supported.
Port C is output only.
Port G serves alternate functions only (not a general I/O port).
Port F serves as digital input only in addition to analog input to the ADC.
Boot Loader capabilities is not supported.
It is not possible to adjust the frequency of the internal calibrated RC Oscillator.
The External Memory Interface can not release any Address pins for general I/O,
neither configure different wait-states to different External Memory Address
sections.
In addition, there are some differences to make it more compatible to ATmega103:
USART has no FIFO buffer, so data overrun comes earlier.
Unused I/O bits in ATmega103 should be written to 0 to ensure same operation in
ATmega128
Timed sequence not required for Watchdog Time-out change.
External Interrupt pins 3 - 0 serve as level interrupt only.
Only EXTRF and PORF exists in MCUCSR.

Features

1 High-performance, Low-power AVR 8-bit Microcontroller
2 Advanced RISC Architecture
133 Powerful Instructions
Most Single Clock Cycle Execution
32 x 8 General Purpose Working Registers + Peripheral Control Registers
Fully Static Operation
Up to 16 MIPS Throughput at 16 MHz
On-chip 2-cycle Multiplier
3 Nonvolatile Program and Data Memories
128K Bytes of In-System Reprogrammable Flash
Endurance: 10,000 Write/Erase Cycles
Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
4K Bytes EEPROM
Endurance: 100,000 Write/Erase Cycles
4K Bytes Internal SRAM
Up to 64K Bytes Optional External Memory Space
Programming Lock for Software Security
SPI Interface for In-System Programming
4 JTAG (IEEE std. 1149.1 Compliant) Interface
Boundary-scan Capabilities According to the JTAG Standard
Extensive On-chip Debug Support
Programming of Flash, EEPROM, Fuses and Lock Bits through the JTAG Interface
5 Peripheral Features
Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
Two Expanded 16-bit Timer/Counters with Separate Prescaler, Compare Mode and
Capture Mode
Real Time Counter with Separate Oscillator
Two 8-bit PWM Channels
6 PWM Channels with Programmable Resolution from 2 to 16 Bits
Output Compare Modulator
8-channel, 10-bit ADC
8 Single-ended Channels
7 Differential Channels
2 Differential Channels with Programmable Gain at 1x, 10x, or 200x
Byte-oriented Two-wire Serial Interface
Dual Programmable Serial USARTs
Master/Slave SPI Serial Interface
Programmable Watchdog Timer with On-chip Oscillator
On-chip Analog Comparator
6 Speed Grades
0 - 8 MHz for ATmega128L
0 - 16 MHz for ATmega12
7 I/O and Packages
53 Programmable I/O Lines
64-lead TQFP and 64-pad QFN/MLF
8 Operating Voltages
2.7 - 5.5V for ATmega128L
4.5 - 5.5V for ATmega128
9 Special Microcontroller Features
Power-on Reset and Programmable Brown-out Detection
Internal Calibrated RC Oscillator
External and Internal Interrupt Sources
Six Sleep Modes: Idle, ADC Noise Reduction, Powersave,Power -down, Standby, and Extended Standby
Software Selectable Clock Frequency
Global Pull-up Disable