Product Summary

The ATF1508ASV(L) is a high-performance, high-density complex programmable logic
device (CPLD) that utilizes Atmel proven electrically-erasable technology. With 128
logic macrocells and up to 100 inputs, it easily integrates logic from several TTL, SSI,
MSI, LSI and classic PLDs.
The ATF1508ASV(L) has up to 96 bi-directional I/O pins and four dedicated input pins,
depending on the type of device package selected. Each dedicated pin can also serve
as a global control signal, register clock, register reset or output enable. Each of these
control signals can be selected for use individually within each macrocell.
Each of the 128 macrocells generates a buried feedback that goes to the global bus.
Each input and I/O pin also feeds into the global bus. The switch matrix in each logic
block then selects 40 individual signals from the global bus. Each macrocell also generates a foldback logic term that goes to a regional bus.Cascade logic between
macrocells in the ATF1508ASV(L) allows fast, efficient generation of complex logic functions. The ATF1508ASV(L) contains eight such logic chains, each capable of creating
sum term logic with a fan-in of up to 40 product terms.
The ATF1508ASV(L) macrocell, shown in Figure 1, is flexible enough to support highlycomplex logic functions operating at high-speed. The macrocell consists of five sections:
product terms and product term select multiplexer, OR/XOR/CASCADE logic, a flip-flop,
output select and enable, and logic array inputs.
Unused macrocells are automatically disabled by the compiler to decrease power consuption-A security fuse,when programmed,protects the contents of the
ATF1508ASV(L). Two bytes (16 bits) of User Signature are accessible to the user for
purposes such as storing project name, part number, revision or date. The User Signature is accessible regardless of the state of the security fuse.
The ATF1508ASV(L) device is an in-system programmable (ISP) device. It uses the
industry-standard 4-pin JTAG interface (IEEE Std. 1149.1), and is fully-compliant with
JTAG Boundary-scan Description Language (BSDL). ISP allows the device to be programmed without removing it from the printed circuit board. In addition to simplifying the
manufacturing flow, ISP also allows design modifications to be made in the field via
software

Parametrics

Temperature Under Bias....................... -40C to +85

Storage Temperature ........................... -65C to +150

Voltage on Any Pin with Respect to Ground .....................-2.0V to +7.0V(1)

Voltage on Input Pins with Respect to Ground During Programming.........................-2.0V to +14.0V(1)

Programming Voltage with Respect to Ground ..........................-2.0V to +14.0V(1)

Features

(1) High-density, High-performance, Electrically-erasable Complex Programmable Logic Device 3.0V to 3.6V Operating Range 128 Macrocells 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell 84, 100, 160 Pins  15 ns Maximum Pin-to-pin Delay Registered Operation up to 77 MHz Enhanced Routing Resources;
(2) Flexible Logic Macrocell D/T/Latch Configurable Flip-flops Global and Individual Register Control Signals Global and Individual Output Enable Programmable Output Slew Rate Programmable Output Open Collector Option Maximum Logic Utilization by Burying a Register within a COM Output;
(3) Advanced Power Management Features Automatic 5 A Standby for Version Pin-controlled 100 A Standby Mode Programmable Pin-keeper Inputs and I/Os Reduced-power Feature per Macrocell;
(4) Available in Commercial and Industrial Temperature Ranges;
(5) Available in 84-lead PLCC and 100-lead PQFP and TQFP and ; 160-lead PQFP Packages;
(6) Advanced EE Technology 100% Tested Completely Reprogrammable 10,000 Program/Erase Cycles  20 Year Data Retention 2000V ESD Protection 200 mA Latch-up Immunity ;
(7) JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported;
(8) Fast In-System Programmability (ISP) via JTAG;
(9) PCI-compliant;
(10)Security Fuse Feature;
(11) Green (Pb/Halide-free/RoHS Compliant) Package Option

Image Part No Mfg Description Data Sheet Download Pricing
(USD)
Quantity
ATF1508ASVL-20AU100
ATF1508ASVL-20AU100

Atmel

CPLD - Complex Programmable Logic Devices CPLD 128 MACROCELL 3.3V 20NS IND TEMP

Data Sheet

0-1: $2.40
1-10: $2.33
10-25: $2.17
25-100: $2.03
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(USD)
Quantity
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ATF1040

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ATF1500A-10AC

Atmel

CPLD - Complex Programmable Logic Devices CPLD 32 MACROCELL CMPTBLE w/F1500

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CPLD - Complex Programmable Logic Devices CPLD 32 MACROCELL 5V 10NS IND TEMP

Data Sheet

0-495: $1.47