Product Summary
The XC95288-20HQ208C0 CPLD family provides advanced in-system programming and test capabilities for high performance, general purpose logic integration. The XC95288-20HQ208C is in-system programmable for a minimum of 10,000 program/erase cycles. Extensive IEEE 1149.1 (JTAG) boundary-scan support is also included on all family members The XC95288-20HQ208C is a 3.3V CPLD targeted for high-performance, low-voltage applications in leading-edge communications and computing systems. The XC95288-20HQ208C is comparised of 1654V18 Function Blocks, providing 6,400 usable gates with propagation delays of 6ns. To help reduce power dissipation, each macrocell in a the XC95288-20HQ208C device may be configured for low-power mode (from the default high-performance mode) .
Parametrics
XC95288-20HQ208C absolute maximum ratings: (1) Supply voltage relative to GND VCC: -0.5V to 4.0V; (2) Input voltage relative to GND VIN: -0.5V to 5.5V; (3) Voltage applied to 3-state output VTS: -0.5V to 5.5V; (4) Storage temperature (ambient) TSTG: -65°C to +150°C; (5) Maximum soldering temperature (10s@1/16in.=1.5mm) TSOL: +260°C ; (6) Junction temperature TJ: +150°C.
Features
XC95288-20HQ208C features: (1) 6ns pin-to-pin logic delays; (2) System frequency upto 208MHz; (3) Optimized for high-performance 3.3V systems; (4) Low power operation; (5) In-system programmable; (6) Input hysteresis on all user and boundary-scan pin inputs.
Diagrams
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XC95288-20HQ208C |
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