MBM29F800TA-90PFTN-SFK

Product Summary

The MBM29F800TA/BA is a 8M-bit, 5.0 V-only Flash memory organized as 1M bytes of 8 bits each or 512K
words of 16 bits each. The MBM29F800TA/BA is offered in a 48-pin TSOP(I) and 44-pin SOP packages. This
device is designed to be programmed in-system with the standard system 5.0 V VCC supply. 12.0 V VPP is not
required for write or erase operations. The devices can also be reprogrammed in standard EPROM programmers.
The standard MBM29LV800TA/BA offers access times 55 ns and 90 ns, allowing operation of high-speed
microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE), write
enable (WE), and output enable (OE) controls.
The MBM29F800TA/BA is pin and command set compatible with JEDEC standard E2
PROMs. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input
to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally
latch addresses and data needed for the programming and erase operations. Reading data out of the devices
is similar to reading from12.0 V Flash or EPROM devices.
The MBM29F800TA/BA is programmed by executing the program command sequence. This will invoke the
Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths
and verifies proper cell margin. Typically, each sector can be programmed and verified in less than 0.5 seconds.
Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase
Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed
before executing the erase operation. During erase, the device automatically times the erase pulse widths and
verifies proper cell margin.
Any individual sector is typically erased and verified in 1.0 second (if already completely preprogrammed.).
The devices also features a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. The MBM29F800TA/BA is erased when shipped from the factory.
The devices features single 5.0 V power supply operation for both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low VCC detector automatically
inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7,
by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase cycle has been
completed, the device internally resets to the read mode.
Fujitsu Flash technology combines years of EPROM and E2.

Parametrics

8M (1M 8/512K 16) BI

Features

(1)Single 5.0 V read, write, and erase;
(2)Minimizes system level power requirements;
(3)Compatible with JEDEC-standard commands;
(4)Uses same software commands as E2;
(5)PROMs;
(6)Compatible with JEDEC-standard world-wide pinouts;
(7)48-pin TSOP(I) (Package suffix: PFTN Normal Bend Type, PFTR Reversed Bend Type);
(8)44-pin SOP (Package suffix: PF);
(9)Minimum 100,000 write/erase cycles;
(10)High performance;
(11)55 ns maximum access time;
(12)Sector erase architecture;
(13)One 16K byte, two 8K bytes, one 32K byte, and fifteen 64K bytes.;
(14)Any combination of sectors can be concurrently erased. Also supports full chip erase.;
(15)Boot Code Sector Architecture;
(16)T = Top sector;
(17)B = Bottom sector;
(18)Embedded EraseTM;
(19)Algorithms;
(20)Automatically pre-programs and erases the chip or any sector;
(21)Embedded ProgramTM;
(22)Algorithms;
(23)Automatically writes and verifies data at specified address; (24) Data Polling and Toggle Bit feature for detection of program or erase cycle completion;
(25)Ready/Busy output (RY/BY);
(26)Hardware method for detection of program or erase cycle completion;
(27)Low Vcc write inhibit 3.2 V;
(28)Erase Suspend/Resume;
(29)Suspends the erase operation to allow a read data in another sector within the same device;
(30)Hardware RESET pin;
(31)Resets internal state machine to the read mode;
(32)Sector protection;
(33)Hardware method disables any combination of sectors from write or erase operations;
(34)Temporary sector unprotection;
(35)Temporary sector unprotection via the RESET pin